A reconfigurable logic circuit (reconfigurable array) is composed by arranging programmable cells in an array. Then, each programmable cell includes a logic block for performing various operations, and a programmable routing resource that programmably connects an input and an output of the logic block according to configuration data.
FIG. 19 shows a logic block 200 of a reconfigurable logic circuit disclosed in PTL 1. The logic block disclosed in PTL 1 is a configuration in which outputs 221A and 221B of preposition logics 220A and 220B are respectively connected to argument inputs A and B of a full adder 230. In the full adder 230, CI is a carry input (231), CO is a carry output (232), and S is a summing output (233).
The preposition logic 220 (preposition logics 220A and 220B are collectively referred to as the preposition logic 220.) inputs inputs 210A and 210B of the preposition logic. The preposition logic 220 is a block which can perform various logical operations. In the case of a relatively small-scale logical operation with not many numbers of inputs, by combining the functions of the two preposition logics 220A and 220B, and the full adder 230, a logical circuit can be realized by one logic block 200.
On the other hand, in the case of a large-scale logic operation with the number of inputs of a certain extent or more, it is difficult to realize the logic circuit by one logic block. In this case, a logic circuit in which a plurality of logic blocks 200—i are connected as shown in FIG. 20 is used. In the logic circuit shown in FIG. 20, a carry output CO and a carry input CI of the plurality of logic blocks 200—i (i is an integer) are connected in cascade, and a ripple carry is composed. Then, a multi-bit full adder is formed.
In FIG. 20, one preposition logic 220B of each logic block 200—i (i is an integer) is configured to output a fixed logic value 0 or 1. For example, when configuring in a way that the fixed logic value as shown in FIG. 21 is provided to the argument input B of each full adder 230, FIGS. 21 and 22 will be equivalent circuit. The reason is that when the fixed logic value 0 is provided to one input of the full adder 230, the carry output CO outputs a logical AND of the remaining two inputs, while when the fixed logic value 1 is provided to one input of the full adder 230, the carry output CO outputs a logical OR of the remaining two inputs. In this way, it is possible to compose the circuit as shown in FIG. 22 in which the plurality of preposition logics 220 are connected in cascade by the logical AND and the logical OR.